Я пытаюсь запустить микроконтроллер Atmel SAM D20 на частоте 48 МГц, используя внутренний генератор (OCM8M) и цифровую схему автоподстройки частоты (DFLL48M). Все, чего я добиваюсь, это тупиковая ситуация с процессором, даже я использую простой проект «Atmel Start».
Я долго искал, но не нашел ни примеров, ни даже описания, как этого добиться. Все ссылается на какой-то другой источник, но ни один источник не объясняет процесс подробно.
Как правильно перевести ЦП во внутренний режим 48 МГц?
Есть ли где-нибудь подробные примеры или пояснения? Я пропустил важный источник?
Любая помощь приветствуется. Любые примеры кода приветствуются на любом языке.
Правильная последовательность запуска Atmel SAM D20 на частоте 48 МГц без внешнего генератора и с использованием только DFLL48M и OSC8M показана в приведенном ниже примере кода.
void initializeSystemFor48MHz()
{
// Change the timing of the NVM access
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val; // 1 wait state for operating at 2.7-3.3V at 48MHz.
// Enable the bus clock for the clock system.
PM->APBAMASK.bit.GCLK_ = true;
// Initialise the DFLL to run in closed-loop mode at 48MHz
// 1. Make a software reset of the clock system.
GCLK->CTRL.bit.SWRST = true;
while (GCLK->CTRL.bit.SWRST && GCLK->STATUS.bit.SYNCBUSY) {};
// 2. Make sure the OCM8M keeps running.
SYSCTRL->OSC8M.bit.ONDEMAND = 0;
// 3. Set the division factor to 64, which reduces the 1MHz source to 15.625kHz
GCLK->GENDIV.reg =
GCLK_GENDIV_ID(3) | // Select generator 3
GCLK_GENDIV_DIV(64); // Set the division factor to 64
// 4. Create generic clock generator 3 for the 15KHz signal of the DFLL
GCLK->GENCTRL.reg =
GCLK_GENCTRL_ID(3) | // Select generator 3
GCLK_GENCTRL_SRC_OSC8M | // Select source OSC8M
GCLK_GENCTRL_GENEN; // Enable this generic clock generator
while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
// 5. Configure DFLL with the
GCLK->CLKCTRL.reg =
GCLK_CLKCTRL_ID_DFLL48M | // Target is DFLL48M
GCLK_CLKCTRL_GEN(3) | // Select generator 3 as source.
GCLK_CLKCTRL_CLKEN; // Enable the DFLL48M
while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
// 6. Workaround to be able to configure the DFLL.
SYSCTRL->DFLLCTRL.bit.ONDEMAND = false;
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
// 7. Change the multiplication factor.
SYSCTRL->DFLLMUL.bit.MUL = 3072; // 48MHz / (1MHz / 64)
SYSCTRL->DFLLMUL.bit.CSTEP = 1; // Coarse step = 1
SYSCTRL->DFLLMUL.bit.FSTEP = 1; // Fine step = 1
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
// 8. Start closed-loop mode
SYSCTRL->DFLLCTRL.reg |=
SYSCTRL_DFLLCTRL_MODE | // 1 = Closed loop mode.
SYSCTRL_DFLLCTRL_QLDIS; // 1 = Disable quick lock.
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
// 9. Clear the lock flags.
SYSCTRL->INTFLAG.bit.DFLLLCKC = 1;
SYSCTRL->INTFLAG.bit.DFLLLCKF = 1;
SYSCTRL->INTFLAG.bit.DFLLRDY = 1;
// 10. Enable the DFLL
SYSCTRL->DFLLCTRL.bit.ENABLE = true;
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
// 11. Wait for the fine and coarse locks.
while (!SYSCTRL->INTFLAG.bit.DFLLLCKC && !SYSCTRL->INTFLAG.bit.DFLLLCKF) {};
// 12. Wait until the DFLL is ready.
while (!SYSCTRL->INTFLAG.bit.DFLLRDY) {};
// Switch the main clock speed.
// 1. Set the divisor of generic clock 0 to 0
GCLK->GENDIV.reg =
GCLK_GENDIV_ID(0) | // Select generator 0
GCLK_GENDIV_DIV(0);
while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
// 2. Switch generic clock 0 to the DFLL
GCLK->GENCTRL.reg =
GCLK_GENCTRL_ID(0) | // Select generator 0
GCLK_GENCTRL_SRC_DFLL48M | // Select source DFLL
GCLK_GENCTRL_IDC | // Set improved duty cycle 50/50
GCLK_GENCTRL_GENEN; // Enable this generic clock generator
while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
}
Это код C++ для Atmel Studio. Для этого требуется только включение "sam.h" и ничего больше.
Вот код запуска из среды разработки Arduino для Arduino Zero, основанный на SAMD21G18. Должно быть достаточно похоже
/**
* \brief SystemInit() configures the needed clocks and according Flash Read Wait States.
* At reset:
* - OSC8M clock source is enabled with a divider by 8 (1MHz).
* - Generic Clock Generator 0 (GCLKMAIN) is using OSC8M as source.
* We need to:
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
* 2) Put XOSC32K as source of Generic Clock Generator 1
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
* 4) Enable DFLL48M clock
* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
* 6) Modify PRESCaler value of OSCM to have 8MHz
* 7) Put OSC8M as source for Generic Clock Generator 3
*/
// Constants for Clock generators
#define GENERIC_CLOCK_GENERATOR_MAIN (0u)
#define GENERIC_CLOCK_GENERATOR_XOSC32K (1u)
#define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
#define GENERIC_CLOCK_GENERATOR_OSC8M (3u)
// Constants for Clock multiplexers
#define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
void SystemInit( void )
{
/* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
/* Turn on the digital interface clock */
PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
/* ----------------------------------------------------------------------------------------------
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
*/
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
{
/* Wait for oscillator stabilization */
}
/* Software reset the module to ensure it is re-initialized correctly */
/* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
* CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
*/
GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
{
/* Wait for reset to complete */
}
/* ----------------------------------------------------------------------------------------------
* 2) Put XOSC32K as source of Generic Clock Generator 1
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* Write Generic Clock Generator 1 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
*/
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
GCLK_CLKCTRL_CLKEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 4) Enable DFLL48M clock
*/
/* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
/* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0 ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK/VARIANT_MAINOSC) ) ; // External 32KHz is the reference
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* Write full configuration to DFLL control register */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
SYSCTRL_DFLLCTRL_WAITLOCK |
SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* Enable the DFLL */
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
{
/* Wait for locks flags */
}
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* Write Generic Clock Generator 0 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/* ----------------------------------------------------------------------------------------------
* 6) Modify PRESCaler value of OSC8M to have 8MHz
*/
SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_1_Val ;
SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
/* ----------------------------------------------------------------------------------------------
* 7) Put OSC8M as source for Generic Clock Generator 3
*/
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
/* Write Generic Clock Generator 3 configuration */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
GCLK_GENCTRL_GENEN ;
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
{
/* Wait for synchronization */
}
/*
* Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
* There values are normally the one present after Reset.
*/
PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
SystemCoreClock=VARIANT_MCK ;
/* ----------------------------------------------------------------------------------------------
* 8) Load ADC factory calibration values
*/
// ADC Bias Calibration
uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
// ADC Linearity bits 4:0
uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
// ADC Linearity bits 7:5
linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
/*
* 9) Disable automatic NVM write operations
*/
NVMCTRL->CTRLB.bit.MANW = 1;
}
Я заставил ATSAMD10 работать с тактовой частотой 48 МГц, с кодом запуска Atmel, установив состояние ожидания NVM на 1 в конфигурации ЦП. При значении 0 (по умолчанию) ЦП останавливается.
перья